Method and apparatus for azimuth bias error correction of sequential-observer detectors

ABSTRACT

A system is disclosed for the correction of azimuth bias error in sequential-observer detectors for surveillance radar systems which assume an average value of azimuth bias in declaring the leading and trailing edges of a target. After normal beamsplitting, the apparent azimuth of the target is corrected by subtracting the effect of half the sweeps that occurred without a video return while searching for the leading edge. Each such sweep has the effect of delaying declaration of a leading edge by one or two sweeps, depending on the pattern of video returns received.

United States Patent Inventors Richard D. Steiugart METHOD AND APPARATUSFOR AZIMUTH BIAS ERROR CORRECTION OF SEQUENTIAL- llll 3,579,237

Assistant Examiner-Malcolm F. Hubler Attorneys-James K. Haskell andWalter J. Adam ABSTRACT: A system is disclosed for the correction ofazimuth bias error in sequential-observer detectors for surveillanceradar systems which assume an average value of azimuth bias in declaringthe leading and trailing edges of a target. g After normalbeam-splitting, the apparent azimuth of the tar- U.S. Cl 343/16, get iscorrected by subtracting the effect of half. the sweeps 343/5 thatoccurred without a video return while searching for the Int. Cl G0ls9/02 leading edge.. Each such sweep has the effect of delaying Field ofSearch ..343/5 (DP), declaration of a leading edge by one or two sweeps,depending 7 (RS), 10, l l, 16 on the pattern of video returns received.

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. Patented "'May 18,1971

5 Sheets-Sheet 1 I Arraznzy Patent ecl May 18, 1971 5 Sheets-:Sheet 5'METHOD P'II'US FOR ERROR CO 1 This invention relates to a method andapparatus for digital target detection and location in surveillanceradar systems and, more particularly, to systems employing asequential-observer detector for determining a beam-split azimuth of atarget.

In contemporary radar systems for surveillance, the raw video returnfrom a target is first quantized, i.e. converted to a series of binarysignals having a value of 1 or depending upon whether or not the rawvideo exceeds a threshold level. A video return (VR) that exceeds thethreshold level of the quantizer is often called a hit. Thus, a VR isdeclared in the form of a signal of predetermined amplitude if, for aradar return, the VR amplitude exceeds the threshold level of thequantizer. For a beacon return, a VR is declared if a valid bracketcoincidence reply is received.

Sequential observer detectors are employed in surveillance radar systemsto automatically detect targets that have a sufficient number of hits ata particular range to satisfy a predetermined criterion. The entiresurveillance area is divided into range intervals often called rangebins, and a sequential-observer detector is associated with each rangeinterval so as to record a history of video returns for the purpose oftarget detection at each range. As the radar antenna scans past a targetat a given range, hits should be received from successive radar sweeps,i.e. from successive azimuths.

Recognizing a pattern of hits from a target at a given range interval inspite of noise in the system is accomplished by proper setting of thecriterion in the sequential-observer detector. For example, if thesequential-observer detector is implemented in the form of an up-downcounter incremented in the form of an up-down counter incremented byhits and decremented by misses (video sweeps not producing hits), thecriterion may be set as a count of six. However, a signal indicating thecriterion has been satisfied merely declares that a target is present atthe given range interval.

To obtain a center bearing on the target, it has been the practice tooperate the up-down counter of the sequential-observer detector for agiven range in reverse once the presence of a target has been declared.Thus, the up-down counter is operated in one mode to find the leadingedge of a target and in an inverter mode to look for the trailing edgeof the target. In the inverted mode, the up-down counter is first resetto 0 and then incremented by each miss and decremented by each hit untilthe same criterion (count of six) is satisfied. At the time a targetreport is sent to a tracking computer for analysis and the sequentialobserver cycle is reinitiated for the same range as the radar antennacontinues to scan in azimuth.

The target report sent to the computer comprises the azimuths of theleading and trailing edges of the target. The tracking computer thencalculates a center bearing on the target by a technique referred to asbeam-splitting. The technique consists essentially of computing theaverage of the leading and trailing edge azimuths.

The problem of locating the center of a target using the beam-splittingtechnique is that there is a delay in declaring the leading and trailingedges of the target since at least six hits must be received before theleading edge is declared and, on the other side of the target, at leastsix misses must occur before the trailing edge is declared. Assumingthat statistically noise will produce spurious hits and misses at thesame rate on each side of the target, the bearing of the target can beeasily corrected in the beam-splitting technique by subtracting from thecomputed average an azimuth bias equal to the angle of six successivesweeps. This technique of compensating for a beam-split azimuth biasassumes an average value of bias for all target return patterns. If theactual return pattern is not the same as the assumed return pattern, anazimuth bias-error is introduced.

Extensive studies have been made of radar and beacon returns todetermine how often target return patterns having spurious misses willinfluence the beam-split azimuth accuracy, and it was found that 23percent of the radar targets and 45 percent of the beacon targets wouldhave beam-split azimuth errors due to spurious misses in the targetreturn patterns. It was further determined that spurious misses aresignificant in automatic video processors only in detennining theleading edge of the target. To affect trailing edge determination,target patterns would require more spurious hits than misses and it wasfound that the probability of a spurious hit is about onetenth theprobability of a spurious miss; consequently only special patterns ofmisses in unique positions of the target pattern actually affecttrailing edge determination.

OBJECTS AND SUMMARY OF THE INVENTION An object of the present inventionis to provide an improved method for beam-split azimuth determination inautomatic video processors.

Another object of the present invention is to provide apparatus fordetermining azimuth bias errors in a beam-splitting system for automaticvideo processors using sequential-observer detectors.

In accordance with the present invention, a sequential-observer detectorutilized for determining leading and trailing edges of a target at agiven range is provided with a separate leading edge delay counter todetermine a more exact value of azimuth bias to compensate for delays indetermining the leading edge of a target. In a preferred embodiment,that is accom-. plished according to the following algorithm. Once amiss has been detected during a search for a target, and a leading edgehas not been declared by a sequential-observer detector, determinewhether or not the sequential-observer detector was at a count of zeroafter the last sweep. If so, reset the leading edge delay counter tozero unless the leading edge delayi counter is at the count of two, inwhich case the count of two is incremented by one, and if not, incrementby two unless the leading edge delay counter has reached a predeterminedmaximum count, in which case the maximum count is retained, or the countis within one unit of the maximum, in which case the counter isincremented by 1. Once the trailing edge of the target has beendeclared, the content of the separate leading edge delay counter istransferred to a computer system for azimuth error correction. Then whenthe apparent azimuth of the target is computed by conventionalbeam-splitting techniques, one-half of the numerical value transferredfrom the leading edge delay counter is subtracted from the apparentazimuth in terms of sweep angles to provide a corrected azimuth for thecenter of the target.

The novel features that are considered characteristic of this inventionare set forth with particularity in the appended claims. The inventionwill best be understood from the following description when read inconnection with the accompanyv ing drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a schematic block diagram ofa radar surveillance system embodying the azimuth bias error correctingmethod of the present invention.

FIG. 2 is an azimuth range-diagram useful in explaining the teachings ofthe invention.

FIG. 3 illustrates examples of target return patterns useful inunderstanding the operation of the present invention.

FIG. 4 is a logic diagram for implementing a sequential-ob serverdetector in the system of FIG. I.

FIG. 5 is a flow chart for the bias error correcting method of thepresent invention.

FIG. 6 is a logic diagram for implementing the fiow chart of FIG. 5 inthe radar surveillance system of FIG. 1.

For a complete understanding of the present invention, the operation ofa surveillance radar system employing a beamsplitting technique willfirst be described with reference to FIG. 1. The radar surveillancesystem includes a transmitterreceiver 10 which generates quantized videosignals together with azimuth and range signals employed to determine atarget azimuth using a sequential-observer detector 1 1.

The sequential-observer detector automatically detects the leading edgeof a target that has a sufficient number of video returns, oftenreferred to as hits, at a particular range to satisfy a predeterminedcriterion. Once that criterion has been satisfied, thesequential-observer detector 11 declares a leading edge and transmits asignal to a leading edge azimuth store control unit 12 to store thecontents of an azimuth counter 13 which is incremented by each azimuthsignal produced during successive sweeps as the radartransmitter-receiver 10 scans in azimuth.

Once a leading edge has been declared, the sequential-observer detector11 is reset and a search for the trailing edge of the target iscommenced. The criterion for the trailing edge is the same as for theleading edge, but as will be more fully appreciated hereinafter,operation of the sequential-observer detector 11 is inverted since, todetect the leading edge of a target, the pattern of hits will determinewhen the leading edge of the target is to be declared, and to determinethe trailing edge of a target, the pattern of misses (where a miss isthe absence of a hit during a sweep at a given range) determines when atrailing edge is to be declared. When a trailing edge is declared, atrailing edge azimuth transfer control unit 14 will cause the contentsof the azimuth of the counter 13 to be stored in a buffer register 15.At the same time, a leading edge azimuth transfer control unit 16 willtransfer the leading edge azimuth from the unit 12 to the bufferregister 15, and a range transfer control unit 17 transfers the contentsof a range counter 18 into the buffer register 15.

FIG. 2 shows an azimuth-range diagram which, together with FIG. 3, willfacilitate understanding the objectives of the present invention. Inthat diagram, it is assumed that the radar transmitter-receiver 10 ofFIG. 1 is located at point 19, and that it transmits a beam atsuccessive azimuths, only fifteen of which are shown at azimuths to 0over half of a 360-scan. In actual practice, the azimuth differencebetween adjacent beams is only a fraction of a degree.

Each transmitted beam commonly referred to as a sweep will be reflectedback to point 19 at different times by targets at different ranges.Therefore a range counter may be employed to sample received signals atsuccessive times during each sweep corresponding to successive rangeinterval R,...R R,, R-,.... Once all range intervals, sometimes referredto an range bins, have been sample, the transmitter-receiver is causedto sweep at the next azimuth by transmitting a radar signal and samplingvideo returns at successive intervals. The video returns may bedisplayed, such as with a conventional cathode ray tube in aplan-position indicator (PPI) arrangement. The result would be apresentation similar to that illustrated in FIG. 3 indicating targets inrange bins R R,,, R,, and R" at different azimuths, such as a target Tin range bin R at azimuth 0,.

It is often desirable to automatically report the presence of targets byrange and bearing only, and not provide a PPI display which requiresinterpretation. Various digital techniques have been devised forlocating the centers of targets, as re ported in An Analysis of SignalDetection and Location By Digital Methods published by G. P. Dinneen andI. S. Reed in IRE Transactions-Information Theory, Mar. 1956, at pages29 to 38. One technique involves the use of an updown counter in asequential-observer detector. The counter is designed to count up when avideo return is received and down when one is not received duringsuccessive sweeps for a given range. A different counter is employed foreach range bin. When a predetermined threshold is reached, a target isdeclared. However, such a declaration can only be associated with theleading edge of the target. To find the center of the target it isnecessary to employ a similar but inverted scheme to identify thetrailing edge. The apparent center of the target is then the averageazimuth of the two declared azimuths, less a fixed bias value associatedwith the threshold count employed.

An ideal video return pattern illustrated in FIG. 3 will clarify thebeam-splitting technique which employs a sequentialobserver detector.The detector is implemented with an updown counter which increments byone for each video return received from a target at a given range, suchas the target T of FIG. 2, and decrements by one for each lack of returnduring a given sweep, except when a count of zero is reached. When apredetermined threshold count is reached by the counter, a target isdeclared. The threshold count selected is determined by the a prioriprobability of noise producing false patterns of hits and misses. Herethe threshold is set at six, but for some environments, it may be set atseven, or five.

In the ideal pattern of FIG. 3, once a hit (VR) is received, asrepresented by a bit I in the first row, misses do not occur duringsubsequent sweeps until the trailing edge of the target is reached.Therefore, after six sweeps, a target leading edge (LED) is declared atthe sweep Q, and the sequential-observer detector (SOD) is reset to zeroinstead of being advanced to the count of six. The process is invertedto search for the tailing edge. When the sequential-observer detectorhas received a total of six misses, a tailing edge is declared (TED) andthe apparent azimuth is found to be Qn+1 by averaging the azimuths Q,and Qn+14- However, it is readily apparent that there is a biasaffecting the determination of target center. Here the actual bias in5.5 sweeps, but as will be seen from patterns A to C of FIG. 3, theactual bias is often exactly six sweeps so that it is convenient to soprogram the target analysis as to always subtract six sweeps from theapparent azimuth.

In pattern A, two hits are followed by a miss. By comparing with theideal pattern, it may be readily seen that the effect of the one miss isa delay of two sweeps in declaring the leading edge of the target.Because of averaging, the net effect is one sweep error in the biascorrected center found by subtracting six sweeps from the apparentcenter. In pattern B, two hits are followed by two misses, each of whichhas an equal effect on the accuracy of the bias corrected center. Inpattern C still another hit-miss sequence is illustrated consisting oftwo misses after a single hit. By comparing the pattern C with the idealpattern, it may be seen that the effect is a delay of three sweeps indeclaring a leading edge, and therefore a net error of 1.5 sweeps in thebias corrected azimuth.

The present invention provides a correction for this biaserror bycounting misses received after an initial hit. Each miss is counted asone or two sweep delays in declaring a target leading edge, dependingupon its position in the VR pattern, until a leading edge is declared,or until a maximum count of seven is reached. That maximum is notcritical; it was determined by the a priori probability that noise wouldnot cause a delay in declaring a leading edge greater than seven sweeps.As in the case of the threshold count, experience in differentenvironments may indicate a large, or smaller, maximum should be used.

A row labeled LEDC in the patterns A, B and C of FIG. 3 represents theleading edge delay counter operation. The count achieved at the time aleading edge is declared, as indicated by the legend LED, is retaineduntil a trailing edge is declared. It is then reported as part of thetarget data. For example, the count of four achieved for pattern B isreported along with the respective azimuths Q,, and 0 of the leading andtrailing edges. The contents of a range counter is also reported tocomplete the target report. A computer then determines the biascorrected center by averaging the azimuths Q, and O and subtracts sixfrom that average for a bias corrected azimuth of 0H By comparing withthe ideal pattern where the bias corrected center is 0 it may be seenthat for the pattern B, the bias error is two sweeps which can becorrected by subtracting half the count of the leading edge delaycounter in terms of sweeps. As a further example, consider the pattern Cwhere the bias corrected center is found to be O By subtracting half ofthe count of three, a bias error corrected azimuth of Q, is found as thecenter of the target.

The centers of other targets are found in the same way, such as oftargets T to T in FIG. 2, even with more than one target in the samerange bin, such as targets T and T This is possi ble because once thetrailing edge of the target T is declared at the azimuth 0;, a targetreport is made and the entire process is repeated. In that regard, itshould be noted that separate counters are provided for the variousrange bins, but as will be more fully appreciated hereinafter, a logicnetwork for only one range bin need be provided if, during a givensweep, numbers are fetched from a storage memory, operated upon andrestored in memory in a predetermined range bin sequence controlled bythe range counter 18 (FIG. 1). The entire range bin sequence is repeatedonce during each sweep. Then once a trailing edge is detected, a targetreport is made by transfer of target data to the bufi'er register 15.

A programmed digital computer 20 samples the buffer registerperiodically or on demand. For example, if leading and trailing edgeshave been declared for a given range, the computer may be notified toread in a target report from the register 15. Alternatively, thecomputer may read target reports from the register only periodically asdetermined by its own internal program. In that case the register 15would be expanded to hold many target reports. Queuing techniquesdeveloped in general data processing systems may be employed toadvantage with such an expanded buffer register, such as advancing allreports as a given one is read, and entering all new reports at the endof the register if a shift register, or some similar form of core memorybuffer, is used.

The antenna azimuths at the times of leading and trailing edgedetections are used by the programmed digital computer 20 to calculatethe azimuth of the target by computing the average of the leading andtrailing edge azimuths and then subtracting the minimum number of radarsweeps required to detect each of the leading and trailing edges of thetarget. For example, the sequential-observer detector 11 implemented inthe form of an up-down counter is incremented by each hit while lookingfor the leading edge of the target and decremented by each miss, exceptwhen a count of zero has been reached, until the detector count reachesa predetermined threshold, such as a count of six. At that time aleading edge is declared, the up-down counter is reset to zero and theprocess is inverted to look for a trailing edge by incrementing thecounter in response to each miss and decrementing the counter inresponse to each hit, except when a count of zero is reached, until thesame threshold is reached, at which time a trailing edge is declared.

When the leading edge of the target is declared, the contents of theazimuths counter 13 are stored by the unit 12 until the trailing edge isdeclared at which time a target report is sent to the programmed digitalcomputer 20 via the buffer register 15 as just described. Since aminimum number of six hits must be received for a given range before theleading edge of the target is declared, and similarly a minimum of sixmisses must be received before a trailing edge is declared, there is aminimum delay of six radar sweeps in obtaining the azimuths used by thebeam-splitting technique of determining the center azimuth of thetarget. Accordingly, the conventional beam-splitting technique calls forsubtracting an azimuth bias of six sweeps when the criterion fordeclaring leading and trailing edges is a count of six.

Thus the prior method of compensating for beam-split azimuth delayassumed the sequential-observer detector 11 introduced an average valueof azimuth bias for all target return patterns detected at a particularradar return threshold level and subtracted this constant bias from thebeam-split azimuth of each target. Consequently an error was introducedif the actual target return pattern was not the same as the assumed oraverage target return pattern as noted hereinbefore with reference toFIG. 3. This azimuth bias error is corrected by the present inventionimplemented in the form of a leading edge delay counter 21 used toaccumulate the effect of lack of returns (misses) of a target on thedeclaration of a leading edge azimuth.

The delay counter 21 monitors both the target returns (hits and misses)and the count of the sequential-observer detector 11, and for each lackof return prior to leading edge determination, the delay counter 21 isincremented by the number of sweeps that the leading edge declarationwill be delayed. Once a leading edge of a target is declared, thecontents of the delay counter 21 are retained until a trailing edge isdeclared. At that time, the contents of the delay counter 21 aretransferred to the buffer register 15, along with other target reportdata, by a delay count transfer control unit 22 as noted hereinbefore.Thus, a leading edge delay count is transferred to the digital computer20 via the buffer register 15. There the leading edge delay count isused to correct the bias error of the beam-split azimuth by subtractinga number of sweep angles equal to half of the leading edge delay count.

Before describing the method for correcting bias error more fully, thegeneral organization of a radar surveillance system employing thebeam-splitting technique will first be more fully described with respectto the manner in which a core memory 25 is used to provide memory cellsfor at least three separate registers at each addressable memorylocations, one location for each range indicated by the range signalfrom the radar transmitter-receiver 10 at a given azimuth. For example,the core memory 25 may have 1,024 addressable memory locations eachcomprising n bits, where n is an arbitrary number such as 12, dividedinto: a first register group of four bits, C C E, and C a secondregister group of three bits C C and C and a third register of aplurality of bits C to C,,.

Each of the memory locations is addressed by a memory access controlunit 26 which receives the contents of the range counter 18 in order toread from and write into successive memory locations corresponding tosuccessive ranges during a given azimuth sweep. The radartransmitter-receiver It) delivers a range signal for each range of agiven azimuth sweep which occurs between azimuths signals that areaccumulated in the azimuth counter 13.

If the radar transmitter-receiver 10 scans 360", the azimuth counter 13will be automatically recycled when m azimuth signal have been counted,where m is an arbitrary number of azimuth sweeps per 360scan. Betweenazimuth signals, the range counter 18 will receive a predeterminednumber of range signals to provide successive counts from zero to 1,023.Following the next azimuth signal, the first range signal will recyclethe range counter 18 to zero for the first range bin.

At a given range during a particular azimuth sweep, a word comprisingbits C to C, is read from the memory location of the core memory 25being addressed by the memory access control unit 26. The operation ofthe core memory 25 is conventional in that the word being read is storedin an M-register 27 via sense amplifiers 28.

The M-register is a conventional static register, each bit position ofwhich is set at a time t, in accordance with a binary digit being readfrom a core via one of the sense amplifiers 28. In order to allow fortime delays in switching cores in the memory 25 and driving the senseamplifiers 28 to proper binary levels before setting the M-register attime t,, the memory access control unit 26 is pulsed at a sufficientlyearlier time t for the read operation of the core memory 25 to follow anormal manner at time I Thereafter, the three groups of binary digits Mto M M to M and M to M, are available for the respective operations ofthe sequential-observer detector 11, the leading edge delay counter 21and the leading edge azimuth store control unit 12.

The binary digits M to M comprise the counter digits of thesequential-observer detector 11 for a given range bin. If a hit isreceived while searching for the leading edge of a target, the countrepresented by the signals M to M is incremented by one at a time 1 Thisability of the sequential-observer detector to receive signals M to Mand to make changes in digits stored in the register 27 is indicated bythe double signal transfer paths, one path indicating signal flow fromthe register 27 and the other signal flow to it.

If a hit being counted causes the number being stored in bit positionsM, to M,, of the register 27 to reach six, a leading edge is declared inthe form of a binary l which is stored in bit position M of theM-register by the sequential-observer de tector 11. The leading edgeazimuth store control unit 12 samples the bit position M at time for thepurpose of causing the contents of the azimuth counter to be stored inbit positions M --M, as the word (bit positions M to M,,) are restoredin the memory 25. During subsequent sweeps, the bit 1 in position Mcauses the operation of the sequential-observer detector to be inverted,as by substituting misses for hits in its logic network for incrementingin response to each miss and substituting hits for misses in its logicfor decrementing in response to each hit.

FIG. 4 illustrates an exemplary implementation of thesequential-observer detector 11. It comprises a logic network for bitpositions M to M of the M-register 27. Each position may consist of anR-S flip-flop as shown and identifying by the standar d convention whichincludes identifying true (Q) and false (Q) signals by the samereference characters, such as flip-flop M, having a true output signalM, and a false output signal M,.

Bit positions M, to M, are employed as binary memory elements for theprocess of counting hits and misses, while the flip-flop M is employedto store a signal LED indicating a leading edge has been declared, untila trailing edge is declared, at which time a signal TED removes thesignal LED by causing the flip-flop M to be reset. At time t, of eachcycle for a given range bin, the contents of the flip-flops M to M, arerestored in the core memory 25. Then at time t, of the next cycle forthat range bin, the stored bits are read through sense amplifiers 28into the flip-flop M to M via a bank of AND gates 34. The inputterminals of the AND gates 34 are identified by the letter C, indicatingsignals which appear there are from the core memory. The subscriptassociated with each letter C indicates the bit position of the signalrepresented.

At time t, the contents of the flip-flops M, to M are incremented by oneifa hit (VR) is received and a leading edge has not been declared, i.e.,a binary 0 is stored in the flip-flop M If the contents of theflip-flops M, to M, represent a count of five in binary form, thecontents of the flip-flops are incremented to a count of zero by thenext hit received. At the same time, the flip-flop M is set. The logicnetwork for counting with a radix of five so as to recycle to zero andeffectively propagate a carry into the bit position M consists of a bankof AND gates 35 having their output terminals connected to S and Rterminals of the flip-flops by a bank of OR gates 36. While contents ofthe flip-flops M to M are being incremented by hits, they are also beingdecremented by misses (VR) through a bank of AND gates 37. Once aleading edge of a target is declared by the propagation of a carry" intobit position M logic networks 38 and 39 connected to the outputterminals of the flip-flop M invert the oper ation of the logic networks35 and 37 by substituting misses (VR) for lnts VR) in the logic network35, and hits (VR) for misses (VR) in the logic network 37. Thereafter,when a count of five misses is reached and another miss occurs duringthe next successive sweep, another Zgarry is effectively generated bythe logic function TED= VR M M, M 1 to reset the flip-flop M and set aflip-flop FF, which stores the function TED until the next time t atwhich time it is reset. At the time 1 just prior thereto, an AND gate 29is enabled by the true output terminal (Q) of the flip-flop FF, totransmit a timing signal t, and thereby cause a target report to betransferred to the buffer register 15.

It should be noted that when the logic network 35 produces a signal TED,all of the flip-flops M to M; are reset so that when their contents arerestored through write amplifiers 30 at time 1 they will be zero for anew target identification process. Consequently, no action need be takento reset the sequential-observer detector 11 once a trailing edge of atarget is declared. The only resetting action required is the resettingof flip-flop FF, which is automatically done by the next timing signal twhile the core memory 25 is being addressed for the next range bin viathe memory access control 26.

Returning now to the general description with reference to FIG. 1, attime t2, the contents of the bit positions M. to M, of the register 27are caused to be incremented, reset to zero or held for recirculation bythe leading edge delay counter 21 comprising a logic network illustratedin FIG. 6 if a leading edge has not been declared. Thus, the threeregisters of the sequential-observer detector 11, leading edge delaycounter 21, and leading edge azimuth control unit 12, are comprised offlip-flops M to M, arranged in respective groups M to M M to M and M toM,,.

The output terminals of those groups of flip-flops are connected to therespective delay count transfer control unit 22, leading edge azimuthtransfer control unit 16 and trailing edge azimuth transfer control 14.In that manner, their contents may be transferred to the buffer register15 at time t, if detection of a trailing edge has been declared by thesequential-observer detector in the tom of a signal at an input terminalof an AND gate 29 as just described with reference to FIG. 4.

The output terminals M to M,, of register 27 are also connected to inputterminals of write amplifiers 30. At time t, their contents are restoredin the memory 25 before the range counter 18 is again incremented by arange signal to address the next memory location.

A timing unit 31 provides the four successive timing signals (t t,, andt and distributes them for use in a conventional manner as illustratedin FIG. 1 for synchronizing the steps of: reading the core memory 25;sampling the sense amplifiers 28 to transfer the contents of the corememory location addressed into the M-register 27; altering the contentsof bit positions M to M and restoring in the same core memory locationthe contents of bit positions M to M,, through the write amplifiers 30,except that if a bit 1 is stored in position M at time t2, the contentsof the azimuth counter 13 are stored in place of bit positions M to M,,.That is readily accomplished by two banks of AND gates (not shown), afirst bank normally enabled by a flip-flop FF: (FIG. 4) forrecirculation until it is set to temporarily store an LED signal once aleading edge is declared, and a second bank of AND gates enabled by theflipfiop FF, while it is set for a period from time t, to the next timet At the intervening time t;,, the contents of the azimuth counter 13 isstored in the memory 25 in place of the contents of the flip-flops M toM,,.

When a target report is transferred to the buffer register 15 inresponse to a signal TED, it is necessary that the leading edge delaycounter 21 be cleared. That is accomplished by connecting each of theflip-flops M to M, to a different input terminal of write amplifiers 30by a separate inhibit gate represented in FIG. 1 by a single gate 33inhibited by the signal TED which enables the AND gate 29.

The bit positions M to M, of the leading edge azimuth store control unit12 need not be reset since the leading edge azimuth count beingtransferred to the buffer register at that time will be replaced by adifferent azimuth count when the next leading edge is declared for thatrange. Thus, once an azimuth count has been stored through the leadingedge azimuth store control unit 12, it is recirculated through the corememory 25 even after it is transferred to the buffer register 15 untilit is replaced by a different azimuth count.

As will be seen from a description of the detailed logic network for theleading edge delay counter 21, a number stored in its bit positions M toM is altered during each successive sweep at time t,, unless a leadingedge has been declared or a count of seven has been reached. Then attime t, the contents of bit positions M to M, are restored in the corememory 25. Once a leading edge has been declared, the contents arerecirculated without alteration each time the same memory location isaddressed by the range counter 18 until a trailing edge is declared forthat range. At that time the contents of the bit positions M, to M aretransferred to the buffer register 15 as noted hereinbefore.

It should be noted that the general organization illustrated in FIG. land the logic network of the sequential-observer detector 11 shown inFIG. 4 are by way of example only. Other organizations for a radarsurveillance system employing the beam-splitting technique may beimproved by a similar leading edge delay counter which may beimplemented as shown in FIG. 6 or in a difierent manner to meet therequirements of different operating environments. Thus, the organizationdescribed with reference to FIG. 1 is intended to be justrepresentative; particular details have been give only to provide anoperating environment for the illustrative logic diagram of FIG. 6.

The broadest aspects of the present invention may best be understoodfrom the following description of the flow chart illustrated in FIG. 5which not only disclosed a method of providing an azimuth bias errorcorrection but also defines details of implementation for any operatingenvironment. For example, the flow chart of FIG. 5 has been translatedinto the logic diagram of FIG. 6 for the organization of a surveillanceradar postulated in FIG. 1 as an exemplary environment for the presentinvention.

A few preliminary examples will facilitate understanding the flow chartof FIG. 5. In the first example, an ideal leading edge pattern isasstuned comprising an uninterrupted series of hits as shown in FIG. 3.The sequential-observer detector will receive each hit and beincremented by one as the radar transmitter-receiver scans throughsuccessive sweeps until a count of six is reached by thesequential-observer detector, at which time an LED signal is general andthe sequential-observer de tector is reset to zero.

The sequential-observer detector remains reset at zero until the firstmiss occurs at which time it is incremented. Thereafter, thesequential-observer detector is incremented by misses and decremented byhits until a count of six is reached. At that time a trailing edge isdeclared by the generation of a signal TED. Meantime, since an idealreturn pattern has been assumed, the leading edge delay counter remainsreset at zero so that the beam-split azimuth is the average of theazimuths of the leading and trailing edges detected, and thebias-compensated, beam-split azimuth is that average less the angle ofsix sweeps. That bias compensation is automatically made at the time theaverage is computed. A bias-error correction is also made by subtractingone-half of the contents of the leading edge delay counter, but in thecase of an ideal return that correction is zero.

Next assume a target return pattern having a miss following twosuccessive hits as in the typical pattern A of FIG. 3. The operation ofthe sequential-observer detector and the leading edge delay counter inresponse to that pattern are both shown in FIG. 3. It should be notedthat the miss occurs before a leading edge is declared by thesequential-observer detector and while the count in thesequential-observer detector from the last sweep is greater than zero(i.e. not equal to zero). Since the leading edge delay counter has notreached a maximum count of seven and is not within one increment of thatmaximum (i.e. not equal to six), the leading delay counter isincremented by two. Thereafter, since no other miss occurs, the count oftwo is retained even after the leading edge is declared by thesequential-observer detector until the trailing edge of the targetpattern is detected upon the sequential-observer detector beingincremented to a count in excess of six in response to misses. At thattime, the leading edge delay count of two is reported for the declaredleading edge of the target. Accordingly, upon computing the averageazimuth, one sweep angle is subtracted from the average for a biaserrorcorrected beam-split azimuth.

If the return pattern is such that a count of six is reached in theleading edge delay counter before still another miss occurs the leadingedge delay counter is incremented by only one so that when the trailingedge of the target is declared, the biaserror correction reported is themaximum count of seven. A bias-error corrected azimuth would then be theapparent misses occur before the leading edge of the target is declared.

This maximum bias-error correction was derived from an analysis of avery large number of radar target and beacon reports. Less than 1percent of the target reports had more than three misses affectingleading edge detection. The data also showed that it was not necessaryto decode all possible combinations of hits and misses.

Trailing edge determination using the sequential-observer detector wasnot noticeably affected by different combinations of hits and misses inthe target return pattern. Therefore, no bias-error correction isrequired for the trailing edge azimuth. However, if further studies ordifferent operating environments should indicate the desirability ofproviding a biaserror correction for the trailing edge azimuth, the samemethod may be employed by simply inverting the operation of the leadingedge delay counter such that hits are substituted for misses and viceversa in its operation, just as in inverting the operation of thesequential-observer detector to look for the trailing edge.

Next consider pattern 18 of FIG. 3 having two successive misses aftertwo successive hits. The first miss increments the leading edge delaycounter by two as in the example of pattern A. The second miss againincrements the leading edge delay counter by two for the same reasonsgiven for incrementing by two in response to the first miss.

Next consider return pattern C of FIG. 3 having two misses after onehit. The first miss increments the leading edge delay counter by two asbefore but the second miss occurs while the sequential-observer detectoris equal to zero and the leading edge delay counter is equal to two. Theexample shows that the delay in declaring the leading edge of the targetis exactly three sweeps; therefore, the azimuth biaserror correctionreported is the count of three. In the previous two examples, the delaysin declaring the leading edges are two and four sweeps, respectively, sothat the bias error corrections are two and four, respectively.

If in the example of pattern C a third miss had occurred in succession,the study of return patterns referred to hereinbefore indicated that thesingle leading hit should be ignored in declaring the leading edge ofthe target; i.e. it is more probable that the first hit is due to noiseand not due to a target. Therefore, if a third miss occurs while thesequential-observer counter is equal to zero and the count of theleading edge delay counter is not equal to two, instead of incrementingthe leading edge delay counter by one or two, the leading edge delaycounter is reset to zero. In that manner, the bias-error correctiondetennination can be reinitiated at the time detection of the leadingedge of the target pattern is reinitiated by the next hit.

In all of these examples, each hit causes the contents of the leadingedge delay counter to be recirculated without alteration until a leadingedge is declared. Thereafter, either a hit or a miss will cause thecontents of the leading edge delay counter to continue to berecirculated unaltered until a pattern of misses causes a trailing edgeto be declared during a given sweep at which time the contents of theleading edge delay counter are reported out to the computer and zero issubstituted for the contents as they are restored in memory.

Referring now to FIG. 5, the flow chart describes the operation of aleading edge delay counter for determining bias-error correction in asurveillance radar system employing a beamsplitting technique accordingto the foregoing examples. The operation starts with a range signalwhich initiates generation of the timing signals t to t,,. If a hitoccurs before the next range signal occurs, the contents of the leadingedge detector are simply recirculated by restoring them in memorywithout alteration at time I Thus the first step indicated by thedecision box 40 is a test for the presence of a'hit. No express testneed be made for that decision; the contents of the leading edge delaycounter are simply restored in memory unaltered after the followingdecisions (made at time fail to indicate that the contents of theleading edge delay counter should be altered. In other words, thecontents of the leading edge delay counter are recirculated unalteredunless some decision is made to alter the contents.

The second step indicated by the box 41 is to determine whether aleading edge has been declared, as signified by the presence of a bit Iin position M If not, the contents of the leading edge delay counter mayrequire one of three possible changes depending upon other decisions tobe made. This test for the presence of a bit 1 in position M may bereadily implemented by including that bit position in the logic networkfor implementing the steps indicated in the negative branch of thedecision box 41.

If a leading edge has been declared, the signal M will enable the logicnetwork connected to the set (S) input terminal of the flip-flop FF ofFIG. 4 thereby implementing a decision box 42 to determine at timewhether a trailing edge is being declared during the current sweep. Ifnot, nothing else happens and at time t the contents of the leading edgedelay counter is restored in memory without alteration, therebyrecirculating the leading edge delay counter. If a trailing edge isbeing declared, the flip-flop FF is set and a signal TED from its true(Q) output terminal thereafter causes the leading edge delay counter tobe stored, i.e. reported as part of the target data, and causes thecontents of the leading edge delay counter to be changed to zero. Asnoted hereinbefore with reference to FIG. 1, that may be easilyimplemented by having the signal TED inhibit the transfer of thecontents of the leading edge delay counter into memory, therebysubstituting zero for the contents of the leading edge delay counter,while causing those contents to be transferred to the buffer register15.

If the decision of the box 41 is negative, (i.e. M =0) the next step isto determine whether the contents of the sequential-observer detectorduring the last sweep was greater than zero (i.e. not equal to zero), asindicated by a decision box 43. If the decision box 43 indicates thecontents of the sequentialobserver detector is equal to zero, the nextstep is to determine whether the contents of the leading edge delaycounter is equal to two, as indicated by a decision box 44. If so, thecontents of the leading edge delay counter is incremented by one beforeit is recirculated (i.e. restored in memory), and if not, the contentsof the leading edge delay counter is reset to zero before it isrecirculated.

If the decision box 43 indicates that the contents of thesequential-observer detector is not equal to zero, the next step is todetermine whether the contents of the leading edge delay counter isequal to seven as indicated by a decision box 45. If so, the contents ofthe leading edge delay counter are recirculated without alteration. Asin the case of the first decision box 40, the decision box 45 need notbe expressly implemented except by way of causing the last decision box46 to fail to initiate either the operation of incrementing the contentsof the leading edge delay counter by one or two, in which case, thecontents of the leading edge delay counter will be restored in memorywithout alteration.

The last decision box 46 simply determines whether the contents of theleading edge delay counter is equal to six. If not, the leading edgedelay counter should be incremented by two, and if so, by only one;otherwise, the contents of the leading edge delay counter may exceed themaximum of seven.

Referring now to FIG. 6 which is a straight-forward implementation ofthe flow chart of FIG. for the environment of FIG. 1, the flip-flops MM,, and M referred to as comprising the register of the leading edgedelay counter 21 are shown as S-R flip-flops, but each may be a J-Kflip-flop since both of its input terminals will not be true at the sametime. The allocation of the flip-flops for the register is such that theleast significant binary digit is stored in the flip-flop M and the mostsignificant digit of a 3-bit binary number is stored in the flipfiop MThe Q-output terminals of the flip-flops are connected to the writeamplifiers 30 each through an inhibit gate shown in FIG. 1 collectivelyas one inhibit gate 33, as noted hereinbefore, such that after theflip-flops M M and M have been set to a new state, as required at timet,, their contents is transferred into memory at time 1, unless atrailing edge has been declared, in which case their contents aretransferred to the buffer register 15 through a delay counter transfercontrol 22.

In practice, the delay count transfer control 22, as well as the othertransfer control functions represented by the blocks 14, 16 and 17, maybe implemented as part of the buffer register 15 by providing as thebuffer register 15 a bank of n delay memory elements commonly referredto as D flip-flops having a single input and an output equal to theinput one bit time earlier. The gate 29 then controls the application ofthe timing signal 2 as a clock pulse to all D flip-flops. Unless anduntil the gate 29 is enabled by a signal TED indicating that a trailingedge has been declared, the D flip-flops of the buffer register 15 willremain in the states into which they were set the last time the gate 29was enabled. Thus, the transfer control functions set forth in theblocks 14, 16, 17 and 22 of FIG. 1 become part of the inherent functionof the buffer register 15 when the buffer register is implemented by Dflip-flops. All the control necessary is then provided by the gate 29.

Once target report data has been transferred into the buffer register15, the data may be read in parallel into the digital computer 20.Following that, the computer may be programmed to reset the bufferregister 15 to zero, but that is not necessary since the contents of thebuffer register 15 will be set in accordance with target report data thenext time a target trailing edge is declared.

To avoid sampling the buffer register 15 at regular intervals, thedigital computer 20 may be connected to the output signal TED of thesequential-observer detector 11 as shown in order that the storedprogram of the digital computer 20 may not read the buffer register 15until a signal TED interrupts the program being executed by the computerthrough a conventional priority-interrupt system internal to thecomputer 20, at which time the digital computer 20 will branch to asubroutine for reading the contents of the buffer register 15 in aconventional manner.

The principle inputs to the logic network of FIG. 6 are the contents offlip-flops M, to M each of which may be an R-S flip-flop, and all ofwhich may be referred to collectively as the contents of the leadingedge delay counter since, at any given time, the binary digitstransferred into those flip-flops from core memory represent the valuesstored by the system for a given range bin.

With such an arrangement the logic network shown in FIG. 6 will do for alarge number of leading edge delay counters, one for each of the 1,024addressable core memory locations. At time t those flip-flops M, t c Mare set via AND gates 50 to correspond to the binary C C C and C C attheir input terminals in a conventional manner characteristic of corememory registers.

Other inputs connected to the flip-flops M to M, via OR gates 41 are thecontents of the flip-flops M M and M which collectively are sometimesreferred to herein as the contents of the sequential-observer detector.At time t the contents of the fiip-flops M to M; are binary digits ofthe hit-miss count stored in the core memory 25 at time 2 of the lastsweep for the range bin indicated by the range counter. In someinstances, the inputs to the logic network of FIG. 6 from the flipflopsM to M of the register 27 are the complements of the binary signalsstored in those flip-flops as indicated by the standard convention of abar over the letter M representing a particular flip-flop as indicatedby the subscript numeral.

The remaining input signals to the logic network of FIG. 6 are thequantized video signal represented by the letters VR (video return) fromthe radar transmitter-receiver 10, and the false output terminal M, ofthe flip-flop M which is set by a signal LED. Thus once a leading edgehas been declared during a given sweep for a particular range, the factthat a leading edge has been declared will be available for subsequentsweeps until a trailing edge is declared, at which time a target reportis transferred out of the flip-flops M M and M The false output terminalM is connected to AND gate 53 and 54 which, together with an AND gate 55and an inverter 56, implement the decision boxes 40, 41, 42 and 43 ofFIG. 5.

The decision box 40 is implemented by the inverter 57 connecting the VRsignal to the AND gates 53 and 54 since, if a hit is received during thecurrent range sweep, the outputs of the AND gates 53 and 54 will remainfalse, thereby disabling all of the rest of the logic network of FIG. 6.Thus, when a timing signal occurs, the rest of the network fails toalter the states of the flip-flops M to M Thereafter, at time thecontents of those flip-flops are restored in memory, therebyrecirculating the leading edge delay count.

The decision box A1 is implemented by the connection of the false outputterminal M to the AND gates 53 and 54 since, once a leading edge hasbeen declared, the flip-flop M (FIG. 4) is set and the AND gates 53 and54 are disabled. This allows the decision box 42 to function by anautomatic recirculation of the contents of the flip-flops M, to M untila trailing edge is declared, at which time the AND gate 29 is enabled totransmit the contents of the flip-flops M to M into the buffer registerat time t;, in accordance with the following transfer control equations:

where 1),, D and D are D-type (delay memory) flip-flops of the resistor15. 3

The next decision box 43 is effectively implemented by the AND gate 55connected directly to the AND gate 53 and to the AND gate 54 by aninverter 56. If the contents of the sequential observer is equal tozero, the AND gate 53 is enabled by the AND gate 55 having all its inputterminals true. If a leading edge has not been declared and a VR signalreceived, the contents of the flip-flops M to M are incremented by oneif those contents are equal to two. AND gate 58 is enabled by all of itsinput terminals being true when those contents are equal to two, i.e.when the contents of the flip-flops M M and M are 0, l, and 0respectively. AND gate 50 then sets the flip-flop M at time 1 therebyincrementing the contents of those flip-flops to three. If the contentsof those flip-flops are not equal to two, the output of the AND gate 58is false. An inverter 60 complements that false output, and therebyenables an AND gate 61 to reset the leading edge delay counter to zeroby resetting the flip flops M to M via OR gates 51 at time t if thecontents of the sequential-ob sgrve deteg tgr is not equal to zero, allof the input terminals M M and M are not true and the AND gate 55 is notenabled. In that event, the AND gate 54 is enabled via the inverter 56to lead into the decision boxes 45 and 46.

The decision box 45 is not expressly implemented, as noted hereinbefore.Only the decision box A6 is implemented by AND gates 62 to 67 and an ORgate 68. AND gate 62 enables AND gate 63 if the contents of theflip-flops M M and M, are equal to six. Then at time t the contents isincremented to seven by setting the least significant bit position MIfthe contents of the flip-flops M M and M,, are not equal to six, asevidenced by either one of the two most significant bit positions M andM not being set, the OR gate 68 enables and AND gate M to increment thecontents of the flip-flops M M and M by two at time t,.

To increment the contents of the leading edge delay counter by two, ANDgates 65 and 66 will switch the flip-flop M to its alternate state.Ifthe flip-flop M is in its binary 0 state (reset), as evidenced by itsoutput terminal M 5 being true, the flipflop M is set via AND gate 65thereby incrementing the contents of the flip-flops M M and M by tworegardless of the state of the flip-flops M and M However, if theflip-flops M is in its binary E state (set), as evidenced by its outputterminal M being true, the flip-flop M is reset via AND gate 66.

Upon resetting theflip-flop 66, a carry is effectively added into thenext more significant bit position by setting the flipflop M via ANDgate 67. This occurs only when the contents of the flip-flops M to Mare'equal to two and three, because if they are equal to six or seven,both output terminals M and M., are false and the AND gates 64 to 67remain disabled at time Instead, the contents are incremented by one ifthey are equal to zero, as noted hereinbefore with reference to ANDgates 62 and 63, or left unaltered if they are equal to seven. In thelatter case, the contents are merely recirculated at time when they arerestored in the core memory 25 of FIG. 1 via write amplifiers 30.

From the foregoing, it should be appreciated that the present inventionenables a target bearing obtained by a beam-splitting technique to becorrected for delay in detecting the leading edge due to the occurrenceof false misses. As noted hereinbefore, the present invention may beextended to further provide for correction of any error due to delay indetecting the trailing edge of a target by inverting the operation ofthe delay counter to provide a weighted count of spurious hits insteadof misses. The correction to be applied to the apparent target centerwould then be half the average of the leading and trailing edge delaycounts. Since the two counts are to be added for averaging, the samedelay counter may be used by simply adding to the stored counts ofspurious misses the weighted counts of spurious hits encountered whilesearching for the trailing edge of a target. To obtain half the averageof the total delay count, that total is then divided by four. Thus,although a particular embodiment of the present invention has beendisclosed in an exemplary environment comprising a real-timesurveillance radar system and a nonreal-tirne computer for carrying outthe beam-splitting calculations, it should be appreciated that thepresent invention is not limited to that particular embodiment andexemplary environment.

We claim: 1. A method for determining error in finding the leading edgeof a target in a radar surveillance system, wherein binary signals areprovided as quantized video returns representing hits and misses from agiven range at successive azimuths as a radar transmitter-receiversweeps in azimuth, and a target leading edge is found by incrementing byone a first counter in response to each hit until a predeterminedthreshold count is reached, at which time a target leading edge isdeclared and decrementing by one said first counter in response to eachmiss except when said second counter is at a count of zero, comprising:

incrementing a second counter by two in response to each miss if thecount of said first counter was not equal to zero after the last sweepat the preceding azimuth;

incrementing said second counter by one in response to each miss if thecount of said first counter wasequal to zero after the last sweep at thepreceding azimuth, and the count of said second counter was at the sametime equal to two; and

resetting said second counter to zero in response to a miss if the countof said first counter was equal to zero after the last sweep at thepreceding azimuth, and the count of said second counter was at the sametime not equal to zero.

2. A method as defined in claim I wherein said first counter is used tofind a trailing edge by inverting its operation to increment on missesand decrement on hits after a leading edge is declared, and-the azimuthsof sweeps during which said leading and trailing edges are declared areused to compute an apparent target center, and the apparent targetcenter is corrected to provide a bias corrected center by subtracting anumber of azimuth sweep angles equal to said threshold count from saidapparent target center, and said bias corrected center is furthercorrected for bias error by subtracting a number of azimuth sweep anglesequal to the count in said second counter during the sweep in which saidleading edge was declared.

3. A method as defined in claim 2 wherein said second counter isincremented in response to misses only until a predetermined maximumcount is reached.

4. A method as defined in claim 3 wherein said maximum count is greaterthan said threshold count.

5. A method as defined in claim 3 wherein said maximum count is greaterthan said threshold count by one.

6. A method as defined in claim 5 wherein said maximum count is an addnumber, and said second counter is incremented by only one in responseto a miss when the count in said second counter is one less than saidmaximum count and said second counter would otherwise be incremented bytwo.

7. In a surveillance radar system having a sequential-observer detectorfor declaring a target leading edge upon an updown counter reaching apredetermined threshold count as it is incremented in response to eachhit, and decremented except when at a count of zero, in response to eachmiss in each sweep at a given range as said radar scans in azimuth, amethod for the correction of azimuth bias error in declaring saidleading edge comprising:

counting sweeps at said given range not producing a hit until saidup-down counter reaches said threshold count, each sweep counted toproduce a leading edge delay count being weighted to account for a delayin declaring a leading edge of a target according to predeterminedpatterns of hits and misses; and

reporting said count with target leading edge azimuth data forsubtraction'of half the number of sweep angles equal to said count froma target azimuth computed from said leading edge azimuth data.

8. A method asdefined in claim 7 wherein each count is weightedaccording to the following predetermined patterns:

when said up-down counter is at a count not equal to zero,

each sweep counted to produce said leading edge delay count has a weightof two until the total leading edge delay count reaches a maximum count,and a weight of one when the total leading edge delay count is one lessthan said maximum;

when said up-down counter is at a count equal to zero, each sweepcounted to produce said leading edge delay count has a weight of one ifthe total leading edge delay count is then equal to two; and

when said up-down counter is at a count equal to zero and the totalleading edge delay count is then not equal to two, the total leadingedge delay count is reset to zero.

9. A method as defined in claim 8 wherein at the time a target leadingedge is declared, said total leading edge delay count then attained isretained together with the azimuth of the sweep during which said targetleading edge is declared until a target trailing edge is declared, whereupon said total leading edge delay count is reported with the azimuthsof sweeps during which said leading and trailing edges were declared astarget data.

10. A method as defined in claim 9 wherein the target center is computedfrom reported target data to be the average of azimuths declared forsaid leading and trailing edges, less a predetermined azimuth bias equalto said threshold count in sweep angles, and less one-half said totalleading edge delay count in sweep angles.

ll. In a radar surveillance system, wherein binary signals are providedas quantized video returns representing hits and misses from a givenrange at successive azimuths as a radar transmitter-receiver sweeps inazimuth in search of a target, the combination comprising:

up-down counting means for counting up in response to hits until athreshold count is reached, and down in response to misses, except whenat a count of zero;

storage means responsive to said up-down counting means for storing as aleading edge the azimuth of the sweep during which said threshold countis reached; and

a leading edge delay counting means for determining error in declaring aleading edge of a target due to misses in the video return patternoccurring before said up-down counter reaches said threshold count byincrementing a leading edge delay count by two in response to each missof the count of said up-down counter was not equal to zero after thelast sweep at the preceding azimuth, incrementing said leading edgedelay count by one in response to each miss if the count of said up-downcounter was equal to zero after the last sweep at the preceding azimuthand said leading edge delay count was at the LII same time equal to two,and setting said leading edge delay count to zero in response to a missif the count of said up-down counter was equal to zero after the lastsweep at the preceding azimuth, and said leading edge delay count was atthe same time not equal to zero.

12. Apparatus as defined in claim 1 1 including:

means for inverting the operation of said up-down counter to count upfrom zero misses and down on hits upon said leading edge azimuth beingstored;

means responsive to said up-down counting means for transmitting atrailing edge azimuth the azimuth of the sweep during which saidthreshold count is reached after said leading edge azimuth is stored;and

means for transmitting simultaneously with said trailing edge azimuthsaid leading edge delay count and said leading edge azimuth from saidleading edge delay counting means and said storage means, respectively,whereby a target center can be computed from transmitted leading andtrailing edge azimuth data and corrected by said transmitted leadingedge delay count.

13. Apparatus as defined in claim 12 wherein said leading edge delaycounter is incremented in response to misses only until a predeterminedmaximum count is reached.

14. Apparatus as defined in claim 13 wherein said maximum count isgreater than said threshold count.

15. Apparatus as defined in claim 13 wherein said maximum count isgreater than said threshold count by one.

16. Apparatus as defined in claim wherein said maximum count is an addnumber, and said leading edge delay counter is incremented by only onein response to a miss when the count therein is one less than saidmaximum count and said leading edge delay counter would otherwise beincremented by two.

17. In a surveillance radar system having an apparatus which declares atarget leading edge upon an up-down counter reaching a predeterminedcount as it is incremented in response to each hit and decremented,except when at a count of zero, in response to each miss in each sweepat a given range as said radar scans in azimuth, and improvement for thecorrection of azimuth bias error comprising:

first means for indicating the azimuth of a sweep when a leading edge ofa target has been declared;

a leading edge delay counting means counting sweeps at said given rangenot producing a hit, each leading edge delay count being weighted toaccount for delay in declaring a leading edge of a target according topredetermined patterns of hits and misses until said indicating meansindicates a leading edge azimuth of a target; and

means for transmitting the leading edge delay count from said countingmeans with said target leading edge azimuth for correction of a targetazimuth derived from said leading edge azimuth.

18. The improvement defined in claim 17 wherein said leading edge delaycounting means comprises:

means for incrementing the contents thereof by two in response to a misswhen said up down counter is at a count not equal to zero, until saidcontents reaches a maximum of seven, and for incrementing by one inresponse to a miss when said up-down counter is at a count of six;

means for incrementing said contents by one when said updown counter isat a count equal to 'zero, if said contents is then equal to two; and

means for resetting said contents to zero when said up-down counter isat a count equal to zero and said contents is then not equal to two.

19. The improvement as defined in claim 18 wherein said apparatusproceeds to search for and declare a trailing edge of a target once aleading edge has been declared, and wherein said leading edge delaycounting means includes:

means responsive to said first means for retaining said contentsunaltered once a leading edge of a target is declared until a targettrailing edge is declared; and

first data transfer means for reporting said contents as a leading edgedelay count upon said trailing edge being declared.

20. The improvement as defined in claim 19 including:

means for counting azimuth sweeps;

storage means for storing the contents of said azimuth sweep countingmeans when a leading edge is declared by said apparatus;

second data transfer means for reporting as target data upon saidtrailing edge being declared the contents of said storage means, and thecontents of said azimuth sweep counting means when said first datatransfer means re ports said contents of said leading edge delaycounting means; and

means for receiving said target data from said first and second datatransfer means.

21. In a surveillance radar system having apparatus for determining thecenter azimuth of a target by first detecting a predetermined number ofsweeps producing hits for determining the leading edge azimuth of saidtarget, then detecting a predetermined number of sweeps producing missesfor determining the trailing edge azimuth of said target, andsubsequently providing a bias correction to said leading and trailingedge azimuths by subtracting a number of sweep angles equal to saidpredetermined number from an average of said leading and trailing edgeazimuths, apparatus for the correction of error in determining theleading edge of said target comprising:

first means for detecting predetermined patterns of sweeps which produceat the leading edge of said target spurious misses that cause a delay inreaching said predetermined number of hits; and

second means responsive to said first means for developing for each ofsaid patterns a compensating number substantially corresponding to theerror in said average of said leading and trailing edge azimuths.

22. Apparatus as defined by claim 21 including computing means andtransfer means for reporting to said computing means said compensatingnumber along with leading and trailing edge azimuths to said computingmeans for determination and correction of said center azimuth of saidtarget.

1. A method for determining error in finding the leading edge of atarget in a radar surveillance system, wherein binary signals areprovided as quantized video returns representing hits and misses from agiven range at successive azimuths as a radar transmitter-receiversweeps in azimuth, and a target leading edge is found by incrementing byone a first counter in response to each hit until a predeterminedthreshold count is reached, at which time a target leading edge isdeclared and decrementing by one said first counter in response to eachmiss except when said second counter is at a count of zero, comprising:incrementing a second counter by two in response to each miss if thecount of said first counter was not equal to zero after the last sweepat the preceding azimuth; incrementing said second counter by one inresponse to each miss if the count of said first counter was equal tozero after the last sweep at the preceding azimuth, and the count ofsaid second counter was at the same time equal to two; and resettingsaid second counter to zero in response to a miss if the count of saidfirst counter was equal to zero after the last sweep at the precedingazimuth, and the count of said second counter was at the same time notequal to zero.
 2. A method as defined in claim 1 wherein said firstcounter is used to find a trailing edge by inverting its operation toincrement on misses and decrement on hits after a leading edge isdeclared, and the azimuths of sweeps during which said leading andtrailing edges are declared are used to compute an apparent targetcenter, and the apparent target center is corrected to provide a biascorrected center by subtracting a number of azimuth sweep angles equalto said threshold count from said apparent target center, and said biascorrected center is further corrected for bias error by subtracting anumber of azimuth sweep angles equal to the count in said second counterduring the sweep in which said leading edge was declared.
 3. A method asdefined in claim 2 wherein said second counter is incremented inresponse to misses only until a predetermined maximum count is reached.4. A method as defined in claim 3 wherein said maximum count is greaterthan said threshold count.
 5. A method as defined in claim 3 whereinsaid maximum count is greater than said threshold count by one.
 6. Amethod as defined in claim 5 wherein said maximum count is an addnumber, and said second counter is incremented by only one in responseto a miss when the count in said second counter is one less than sAidmaximum count and said second counter would otherwise be incremented bytwo.
 7. In a surveillance radar system having a sequential-observerdetector for declaring a target leading edge upon an up-down counterreaching a predetermined threshold count as it is incremented inresponse to each hit, and decremented except when at a count of zero, inresponse to each miss in each sweep at a given range as said radar scansin azimuth, a method for the correction of azimuth bias error indeclaring said leading edge comprising: counting sweeps at said givenrange not producing a hit until said up-down counter reaches saidthreshold count, each sweep counted to produce a leading edge delaycount being weighted to account for a delay in declaring a leading edgeof a target according to predetermined patterns of hits and misses; andreporting said count with target leading edge azimuth data forsubtraction of half the number of sweep angles equal to said count froma target azimuth computed from said leading edge azimuth data.
 8. Amethod as defined in claim 7 wherein each count is weighted according tothe following predetermined patterns: when said up-down counter is at acount not equal to zero, each sweep counted to produce said leading edgedelay count has a weight of two until the total leading edge delay countreaches a maximum count, and a weight of one when the total leading edgedelay count is one less than said maximum; when said up-down counter isat a count equal to zero, each sweep counted to produce said leadingedge delay count has a weight of one if the total leading edge delaycount is then equal to two; and when said up-down counter is at a countequal to zero and the total leading edge delay count is then not equalto two, the total leading edge delay count is reset to zero.
 9. A methodas defined in claim 8 wherein at the time a target leading edge isdeclared, said total leading edge delay count then attained is retainedtogether with the azimuth of the sweep during which said target leadingedge is declared until a target trailing edge is declared, where uponsaid total leading edge delay count is reported with the azimuths ofsweeps during which said leading and trailing edges were declared astarget data.
 10. A method as defined in claim 9 wherein the targetcenter is computed from reported target data to be the average ofazimuths declared for said leading and trailing edges, less apredetermined azimuth bias equal to said threshold count in sweepangles, and less one-half said total leading edge delay count in sweepangles.
 11. In a radar surveillance system, wherein binary signals areprovided as quantized video returns representing hits and misses from agiven range at successive azimuths as a radar transmitter-receiversweeps in azimuth in search of a target, the combination comprising:up-down counting means for counting up in response to hits until athreshold count is reached, and down in response to misses, except whenat a count of zero; storage means responsive to said up-down countingmeans for storing as a leading edge the azimuth of the sweep duringwhich said threshold count is reached; and a leading edge delay countingmeans for determining error in declaring a leading edge of a target dueto misses in the video return pattern occurring before said up-downcounter reaches said threshold count by incrementing a leading edgedelay count by two in response to each miss of the count of said up-downcounter was not equal to zero after the last sweep at the precedingazimuth, incrementing said leading edge delay count by one in responseto each miss if the count of said up-down counter was equal to zeroafter the last sweep at the preceding azimuth and said leading edgedelay count was at the same time equal to two, and setting said leadingedge delay count to zero in response to a miss if the count of saidup-down counter was equal to zero after the last sweep at the precedingazimuth, And said leading edge delay count was at the same time notequal to zero.
 12. Apparatus as defined in claim 11 including: means forinverting the operation of said up-down counter to count up from zeromisses and down on hits upon said leading edge azimuth being stored;means responsive to said up-down counting means for transmitting atrailing edge azimuth the azimuth of the sweep during which saidthreshold count is reached after said leading edge azimuth is stored;and means for transmitting simultaneously with said trailing edgeazimuth said leading edge delay count and said leading edge azimuth fromsaid leading edge delay counting means and said storage means,respectively, whereby a target center can be computed from transmittedleading and trailing edge azimuth data and corrected by said transmittedleading edge delay count.
 13. Apparatus as defined in claim 12 whereinsaid leading edge delay counter is incremented in response to missesonly until a predetermined maximum count is reached.
 14. Apparatus asdefined in claim 13 wherein said maximum count is greater than saidthreshold count.
 15. Apparatus as defined in claim 13 wherein saidmaximum count is greater than said threshold count by one.
 16. Apparatusas defined in claim 15 wherein said maximum count is an add number, andsaid leading edge delay counter is incremented by only one in responseto a miss when the count therein is one less than said maximum count andsaid leading edge delay counter would otherwise be incremented by two.17. In a surveillance radar system having an apparatus which declares atarget leading edge upon an up-down counter reaching a predeterminedcount as it is incremented in response to each hit and decremented,except when at a count of zero, in response to each miss in each sweepat a given range as said radar scans in azimuth, and improvement for thecorrection of azimuth bias error comprising: first means for indicatingthe azimuth of a sweep when a leading edge of a target has beendeclared; a leading edge delay counting means counting sweeps at saidgiven range not producing a hit, each leading edge delay count beingweighted to account for delay in declaring a leading edge of a targetaccording to predetermined patterns of hits and misses until saidindicating means indicates a leading edge azimuth of a target; and meansfor transmitting the leading edge delay count from said counting meanswith said target leading edge azimuth for correction of a target azimuthderived from said leading edge azimuth.
 18. The improvement defined inclaim 17 wherein said leading edge delay counting means comprises: meansfor incrementing the contents thereof by two in response to a miss whensaid up-down counter is at a count not equal to zero, until saidcontents reaches a maximum of seven, and for incrementing by one inresponse to a miss when said up-down counter is at a count of six; meansfor incrementing said contents by one when said up-down counter is at acount equal to zero, if said contents is then equal to two; and meansfor resetting said contents to zero when said up-down counter is at acount equal to zero and said contents is then not equal to two.
 19. Theimprovement as defined in claim 18 wherein said apparatus proceeds tosearch for and declare a trailing edge of a target once a leading edgehas been declared, and wherein said leading edge delay counting meansincludes: means responsive to said first means for retaining saidcontents unaltered once a leading edge of a target is declared until atarget trailing edge is declared; and first data transfer means forreporting said contents as a leading edge delay count upon said trailingedge being declared.
 20. The improvement as defined in claim 19including: means for counting azimuth sweeps; storage means for storingthe contents of said azimuth sweep counting means when a leading edge isdeclared by said apparatus; second dAta transfer means for reporting astarget data upon said trailing edge being declared the contents of saidstorage means, and the contents of said azimuth sweep counting meanswhen said first data transfer means reports said contents of saidleading edge delay counting means; and means for receiving said targetdata from said first and second data transfer means.
 21. In asurveillance radar system having apparatus for determining the centerazimuth of a target by first detecting a predetermined number of sweepsproducing hits for determining the leading edge azimuth of said target,then detecting a predetermined number of sweeps producing misses fordetermining the trailing edge azimuth of said target, and subsequentlyproviding a bias correction to said leading and trailing edge azimuthsby subtracting a number of sweep angles equal to said predeterminednumber from an average of said leading and trailing edge azimuths,apparatus for the correction of error in determining the leading edge ofsaid target comprising: first means for detecting predetermined patternsof sweeps which produce at the leading edge of said target spuriousmisses that cause a delay in reaching said predetermined number of hits;and second means responsive to said first means for developing for eachof said patterns a compensating number substantially corresponding tothe error in said average of said leading and trailing edge azimuths.22. Apparatus as defined by claim 21 including computing means andtransfer means for reporting to said computing means said compensatingnumber along with leading and trailing edge azimuths to said computingmeans for determination and correction of said center azimuth of saidtarget.